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3-3 tm features ? maximum input clock maximum frequency options at v dd = 5v - cdp1802a, ac . . . . . . . . . . . . . . . . . . . . . . . . . 3.2mhz - cdp1802bc . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0mhz maximum input clock maximum frequency options at v dd = 10v - cdp1802a, ac . . . . . . . . . . . . . . . . . . . . . . . . . 6.4mhz minimum instruction fetch - execute times at v dd = 5v - cdp1802a, ac . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 s - cdp1802bc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 s any combination of standard ram and rom up to 65,536 bytes 8 - bit parallel organization with bidirectional data bus and multiplexed address bus 16 x 16 matrix of registers for use as multiple program counters, data pointers, or data registers on - chip dma, interrupt, and flag inputs programmable single - bit output port 91 easy - to - use instructions description the cdp1802 family of cmos microprocessors are 8-bit register oriented central processing units (cpus) designed for use as general purpose computing or control elements in a wide range of stored program systems or products. the cdp1802 types include all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. extensive input/output (i/o) control features are also provided to facili- tate system design. the 1800 series architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized. the 1800 series cpu also provides a synchro- nous interface to memories and external controllers for i/o devices, and minimizes the cost of interface controllers. fur- ther, the i/o interface is capable of supporting devices oper- ating in polled, interrupt driven, or direct memory access modes. the cdp1802a and cdp1802ac have a maximum input clock frequency of 3.2mhz at v dd = 5v. the cdp1802a and cdp1802ac are functionally identical. they differ in that the cdp1802a has a recommended operating voltage range of 4v to 10.5v, and the cdp1802ac a recommended operat- ing voltage range of 4v to 6.5v. the cdp1802bc is a higher speed version of the cdp1802ac, having a maximum input clock frequency of 5.0mhz at v dd = 5v, and a recommended operating voltage range of 4v to 6.5v. ordering information part number temperature range package pkg. no. 5v - 3.2mhz 5v - 5mhz cdp1802ace cdp1802bce -40 o c to +85 o c pdip e40.6 cdp1802acex cdp1802b cex burn-in e40.6 cdp1802acq cdp1802bcq -40 o c to +85 o c plcc n44.65 CDP1802ACD - -40 o c to +85 o c sbdip d40.6 CDP1802ACDx cdp1802bcdx burn-in d40.6 march 1997 file number 1305.2 cdp1802a, cdp1802ac, cdp1802bc cmos 8-bit microprocessors caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
3-4 pinouts 40 lead pdip (package suffix e) 40 lead sbdip (package suffix d) top view 44 lead plcc (package type q) top view figure 1. typical cdp1802 small microprocessor system 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 clock wait clear q sc1 sc0 mrd bus 7 bus 6 bus 5 bus 4 bus 3 bus 2 bus 1 bus 0 v cc n2 n1 n0 v ss 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v dd xtal dma in dma out interrupt mwr tpa tpb ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ef1 ef2 ef3 ef4 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 26 25 24 23 22 21 20 19 18 7 8 9 10 11 12 13 14 15 16 17 sc0 mrd bus 7 bus 6 bus 5 nc bus 4 bus 3 bus 2 bus 1 bus 0 sc1 q clear wait clock nc v dd xtal dma-in dma-out interrupt v cc n2 n1 n0 v ss nc ef4 ef3 ef2 ef1 ma0 mwr tpa tpb ma7 ma6 nc ma5 ma4 ma3 ma2 ma1 cdp1852 input port data cs1 cs2 cdp1852 output port clock cs1 cs2 ma0 - 7 n0 mrd mwr n1 tpb data tpa cdp1802 8 - bit cpu mrd ma0 - 4 mwr cs cdp1824 32 byte ram ma0 - 7 data cdp1833 1k - rom ceo tpa mrd address bus cdp1802a, cdp1802ac, cdp1802bc
3-5 block diagram figure 2. mux ma7ma5ma3ma1 ma0 ma2 ma4 ma6 memory address lines i/o flags alu b d df incr/ decr a r(0).1 r(0).0 r(1).0 r(1).1 r(2).1 r(2).0 r(9).0 r(a).0 r(a).1 r(9).1 r(e).1 r(f).1 r(f).0 r(e).0 register array 8-bit bidirectional data bus latch and decode r xtp i n n1 n0 n2 i/o commands bus 0 bus 1 bus 2 bus 3 bus 4 bus 5 bus 6 bus 7 to instruction decode control and timing logic clock logic i/o requests control ef1 ef3 ef2 ef4 dma out dma in int clear wait clock xtal sco sci q logic tpa tpb mwr mrd system state codes timing cdp1802a, cdp1802ac, cdp1802bc
3-6 absolute maximum ratings thermal information dc supply voltage range, (v dd ) (all voltages referenced to v ss terminal) cdp1802a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +11v cdp1802ac, cdp1802bc. . . . . . . . . . . . . . . . . . . . -0.5v to +7v input voltage range, all inputs . . . . . . . . . . . . . .-0.5v to v dd +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . . 10ma thermal resistance (typical, note 4) ja ( o c/w) jc ( o c/w) pdip . . . . . . . . . . . . . . . . . . . . . . . . . . 50 n/a plcc . . . . . . . . . . . . . . . . . . . . . . . . . . 46 n/a sbdip . . . . . . . . . . . . . . . . . . . . . . . . . 55 15 device dissipation per output transistor t a = full package temperature range . . . . . . . . . . . . . . . 100mw operating temperature range (t a ) package type d . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c package type e and q. . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c storage temperature range (t stg ) . . . . . . . . . . . . -65 o c to +150 o c lead temperature (during soldering) at distance 1/16 1/32 in. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 o c lead tips only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indica ted in the operational sections of this specification is not i mplied. recommended operating conditions t a = -40 o c to +85 o c. for maximum reliability, operating conditions should be selected so that operation is always within the following ranges: parameter test conditions cdp1802a cdp1802ac cdp1802bc units (note 2) v cc (v) v dd (v) min max min max min max dc operating voltage range - - 4 10.5 4 6.5 4 6.5 v input voltage range - - v ss v dd v ss v dd v ss v dd v maximum clock input rise or fall time 4 to 6.5 4 to 6.5 - - - 1 - 1 s 4 to 10.5 4 to 10.5 - 1 - - - - s minimum instruction time (note 3) 5 5 5-5-3.2- s 5 10 4----- s 10 10 2.5 - - - - - s maximum dma transfer rate 5 5 - 400 - 400 - 667 kbytes/s 5 10 -500---- 10 10 - 800 - - - - maximum clock input frequency, f cl , load capacitance (c l ) = 50pf 5 5 dc 3.2 dc 3.2 dc 5 mhz 5 10dc4----mhz 10 10 dc 6.4 - - - - mhz notes: 1. printed circuit board mount: 57mm x 57mm minimum ar ea x 1.6mm thick g10 epoxy glass, or equivalent. 2. v cc must never exceed v dd . 3. equals 2 machine cycles - one fetch and one execute operation for all instructions except long branch and long skip, which re quire 3 machine cycles - one fetch and two execute operations. 4. ja is measured with component mount ed on an evaluation board in free air. cdp1802a, cdp1802ac, cdp1802bc
3-7 static electrical specifications at t a = -40 o c to +85 o c, except as noted parameter symbol test conditions cdp1802a cdp1802ac, cdp1802bc units v out (v) v in (v) v cc , v dd (v) min (note 1) typ max min (note 1) typ max quiescent device current i dd - - 5 - 0.1 50 - 1 200 a - - 10 - 1 200 - - - a output low drive (sink) current i ol 0.4 0, 5 5 1.1 2.2 - 1.1 2.2 - ma (except xtal ) 0.5 0, 10 10 2.2 4.4 - - - - ma xtal 0.4 5 5 170 350 - 170 350 - a output high drive (source) current i oh 4.6 0, 5 5 -0.27 -0.55 - -0.27 -0.55 - ma (except xtal ) 9.5 0, 10 10 -0.55 -1.1 - - - - ma xtal 4.6 0 5 -125 -250 - -125 -250 - a output voltage - 0, 5 5 - 0 0.1 - 0 0.1 v low level v ol - 0, 10 10 - 0 0.1 - - - v output voltage - 0, 5 5 4.9 5 - 4.9 5 - v high level v oh - 0, 10 10 9.9 10 - - - - v input low voltage v il 0.5, 4.5 - 5 - - 1.5 - - 1.5 v 0.5, 4.5 - 5, 10 - - 1 - - - v 1, 9-10--3---v input high voltage v ih 0.5, 4.5 - 5 3.5 - - 3.5 - - v 0.5, 4.5 - 5, 10 4 - - - - - v 1, 9-107-----v clear input voltage v h - - 5 0.4 0.5 - 0.4 0.5 - v schmitt hysteresis - - 5, 10 0.3 0.4 - - - - v - - 10 1.5 2 - - - - v input leakage current i in any input 0, 5 5 - 10 -4 1- 10 -4 1 a 0, 10 10 - 10 -4 1--- a three-state output leakage i out 0, 5 0, 5 5 - 10 -4 1- 10 -4 1 a current 0, 10 0, 10 10 - 10 -4 1--- a operating current cdp1802a, ac at f = 3.2mhz i ddi (note 2) --5-24-24ma cdp1802bc at f = 5.0mhz --5-- --36ma minimum data retention voltage v dr v dd = v dr -22.4- 22.4v data retention current i dr v dd = 2.4v - 0.05 - - 0.5 - a cdp1802a, cdp1802ac, cdp1802bc
3-8 input capacitance c in - 5 7.5 - 5 7.5 pf output capacitance c out - 10 15 - 10 15 pf notes: 1. typical values are for t a = +25 o c and nominal v dd . 2. idle ?00? at m(0000), c l = 50pf. dynamic electrical specifications t a = -40 o c to +85 o c, c l = 50pf, v dd 5%, except as noted parameter symbol test conditions cdp1802a, cdp1802ac cdp1802bc units v cc (v) v dd (v) (note 1) typ max (note 1) typ max propagation delay times clock to tpa, tpb t plh , t phl 5 5 200 300 200 300 ns 5 10 150 250 - - ns 10 10 100 150 - - ns clock-to-memory high-address byte t plh , t phl 5 5 600 850 475 525 ns 5 10 400 600 - - ns 10 10 300 400 - - ns clock-to-memory low-address byte valid t plh , t phl 5 5 250 350 175 250 ns 5 10 150 250 - - ns 10 10 100 150 - - ns clock to mrd t phl 5 5 200 300 175 275 ns 5 10 150 250 - - ns 10 10 100 150 - - ns clock to mrd t plh 5 5 200 350 175 275 ns 5 10 150 290 - - ns 10 10 100 175 - - ns clock to mwr t plh , t phl 5 5 200 300 175 225 ns 5 10 150 250 - - ns 10 10 100 150 - - ns clock to (cpu data to bus) valid t plh , t phl 5 5 300 450 250 375 ns 5 10 250 350 - - ns 10 10 100 200 - - ns static electrical specifications at t a = -40 o c to +85 o c, except as noted (continued) parameter symbol test conditions cdp1802a cdp1802ac, cdp1802bc units v out (v) v in (v) v cc , v dd (v) min (note 1) typ max min (note 1) typ max cdp1802a, cdp1802ac, cdp1802bc
3-9 clock to state code t plh , t phl 5 5 300 450 250 400 ns 5 10 250 350 - - ns 10 10 150 250 - - ns clock to q t plh , t phl 5 5 250 400 200 300 ns 5 10 150 250 - - ns 10 10 100 150 - - ns clock to n (0 - 2) t plh , t phl 5 5 300 550 275 350 ns 5 10 200 350 - - ns 10 10 150 250 - - ns minimum set up and hold times data bus input set up t su 55-2025-20 0ns 5 10 0 50 - - ns 10 10 -10 40 - - ns data bus input hold t h (note 2) 5 5 150 200 125 150 ns 5 10 100 125 - - ns 10 10 75 100 - - ns dma set up t su 55030030ns 5 10 0 20 - - ns 10 10 0 10 - - ns dma hold t h (note 2) 5 5 150 250 100 150 ns 5 10 100 200 - - ns 10 10 75 125 - - ns interrupt set up t su 5 5 -75 0 -75 0 ns 510 -50 0 - - ns 10 10 -25 0 - - ns interrupt hold t h (note 2) 5 5 100 150 75 125 ns 5 10 75 100 - - ns 10 10 50 75 - - ns wait set up t su 5 5 10 50 20 40 ns 5 10 -10 15 - - ns 10 10 0 25 - - ns dynamic electrical specifications t a = -40 o c to +85 o c, c l = 50pf, v dd 5%, except as noted (continued) parameter symbol test conditions cdp1802a, cdp1802ac cdp1802bc units v cc (v) v dd (v) (note 1) typ max (note 1) typ max cdp1802a, cdp1802ac, cdp1802bc
3-10 ef1-4 set up t su 55-3020-30 0ns 5 10 -20 30 - - ns 10 10 -10 40 - - ns ef1-4 hold t h (note 2) 5 5 150 200 100 150 ns 5 10 100 150 - - ns 10 10 75 100 - - ns minimum pulse width times clear pulse width t wl (note 2) 5 5 150 300 100 150 ns 5 10 100 200 - - ns 10 10 75 150 - - ns clock pulse width t wl 5 5 125 150 90 100 ns 5 10 100 125 - - ns 10 10 60 75 - - ns notes: 1. typical values are for t a = +25 o c and nominal v dd . 2. maximum limits of minimum characteristics are the values above which all devices function. timing specifications as a function of t(t = 1/f clock ) at t a = -40 to +85 o c, except as noted parameters symbol test conditions cdp1802a, cdp1802ac cdp1802bc units v cc (v) v dd (v) min (note 1) typ min (note 1) typ high-order memory-address byte set up to tpa time t su 5 5 2t-550 2t-400 2t-325 2t-275 ns 5 10 2t-350 2t250 - - ns 10 10 2t-250 2t-200 - - ns high-order memory-address byte hold after tpa time t h 5 5 t/2-25 t/2-15 t/2-25 t/2-15 ns 5 10 t/2-35 t/2-25 - - ns 10 10 t/2-10 t/2-+0 - - ns low-order memory-address byte hold after wr time t h 5 5 t-30 t+0 t-30 t+0 ns 510t-20t+0- - ns 10 10 t-10 t+0 - - ns cpu data to bus hold after wr time t h 5 5 t-200 t-150 t-175 t-125 ns 5 10 t-150 t-100 - - ns 10 10 t-100 t-50 - - ns dynamic electrical specifications t a = -40 o c to +85 o c, c l = 50pf, v dd 5%, except as noted (continued) parameter symbol test conditions cdp1802a, cdp1802ac cdp1802bc units v cc (v) v dd (v) (note 1) typ max (note 1) typ max cdp1802a, cdp1802ac, cdp1802bc
3-11 required memory access time ad- dress to data t acc 5 5 5t-375 5t-250 5t-225 5t-175 ns 5 10 5t-250 5t-150 - - ns 10 10 5t-190 5t-100 - - ns mrd to tpa t su 5 5 t/2-25 t/2-18 t/2-20 t/2-15 ns 5 10 t/2-20 t/2-15 - - ns 10 10 t/2-15 t/2-10 - - ns note: 1. typical values are for t a = +25 o c and nominal v dd . timing specifications as a function of t(t = 1/f clock ) at t a = -40 to +85 o c, except as noted parameters symbol test conditions cdp1802a, cdp1802ac cdp1802bc units v cc (v) v dd (v) min (note 1) typ min (note 1) typ timing waveforms figure 3. basic dc timing waveform, one instruction cycle fetch (read) execute (write) 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 hi byte low byte hi byte low byte clock address tpa tpb mrd mwr data valid input data valid output data cdp1802a, cdp1802ac, cdp1802bc
3-12 notes: 1. this timing diagram is used to show signal relationshi ps only and does not represent any specific machine cycle. 2. all measurements are referenced to 50% point of the waveforms. 3. shaded areas indicate ?don?t care? or undefined state. multiple transitions may occur during this period. figure 4. timing waveform timing waveforms (continued) clock tpa tpb memory mrd mwr (i/o execution q data from dma interrupt ef 1-4 wait clear request request bus to cpu n0, n1, n2 state data from cpu to bus (memory write cycle) (memory address read cycle) codes cycle) t w 00 10 20 30 40 50 60 70 00 01 11 21 31 41 51 61 71 01 0 1 2 3 4 5 6 7 0 t plh t phl t plh t phl t plh , t phl t su dma sampled (s1, s2, s3) t h address byte high order t phl t plh t su t plh , t phl t plh , t phl t plh t h t plh t h t plh , t phl t plh , t phl t plh , t phl address byte low order t phl t plh t phl t plh t phl t plh t plh data latched in cpu t su t h t su t h t su t h interrupt sampled (s1, s2) flag lines sampled (in s1) any negative transition t su t w t su t h cdp1802a, cdp1802ac, cdp1802bc
3-13 machine cycle timing waveforms (propagation delays not shown) figure 5. general timing waveforms figure 6. non-memory cycle timing waveforms figure 7. memory write cycle timing waveforms clock tpa tpb machine ma cycle 01 23 45 6701 2345 6701 2345 670 cycle n cycle (n + 1) cycle (n + 2) low address high add low address high add low address high add memory read cycle non memory cycle memory read cycle instruction mrd mwr (high) memory output fetch (s0) execute (s1) fetch (s0) execute allowable memory access valid output valid output ?don?t care? or internal delays high impedance state memory output allowable memory access valid output valid output memory read cycle memory write cycle memory read cycle instruction fetch (s0) execute (s1) fetch (s0) execute cpu output off valid data off valid mwr mrd to memory ?don?t care? or internal delays high impedance state cdp1802a, cdp1802ac, cdp1802bc
3-14 figure 8. memory read cycle timing waveforms figure 9. long branch or long sk ip cycle timing waveforms machine cycle timing waveforms (propagation delays not shown) (continued) memory read cycle memory read cycle memory read cycle instruction fetch (s0) execute (s1) fetch (s0) execut e memory output allowable memory access valid output valid output mrd mwr (high) ?don?t care? or internal delays high impedance state valid output memory output allowable memory access valid output valid output memory read cycle memory read cycle memory read cycle instruction fetch (s0) execute (s1) execute (s1) fetch (s 0) mrd mwr (high) ?don?t care? or internal delays high impedance state valid output cdp1802a, cdp1802ac, cdp1802bc
3-15 figure 10. input cycle timing waveforms figure 11. output cycle timing waveforms machine cycle timing waveforms (propagation delays not shown) (continued) clock 01 23 456 70123456 7 memory output allowable memory access valid output tpa tpb machine instruction mrd n0 - n2 data mwr cycle bus memory read cycle memory write cycle valid data from input device n = 9 - f execute (s1) cycle (n + 1) cycle n fetch (s0) note 1 ?don?t care? or internal delays high impedance state (note 1) user generated signal 0 clock 01 23 456 70123456 7 tpa tpb machine instruction cycle execute (s1) cycle (n + 1) cycle n fetch (s0) data bus allowable memory access valid output valid data from memory allowable memory access memory read cycle memory read cycle mrd n0 - n2 data strobe (mrd ? tpb ? n) note 1 ?don?t care? or internal delays high impedance state (note 1) user generated signal 0 n = 1 - 9 cdp1802a, cdp1802ac, cdp1802bc
3-16 figure 12. dma in cycle timing waveforms figure 13. dma out cycle timing waveforms machine cycle timing waveforms (propagation delays not shown) (continued) clock 01 23 456701234567 01 23 tpa tpb machine i nstruction dma-in mrd mwr memory data bus cycle output 45 67 note 1 memory read cycle memory read, write memory write cycle or non-memory cycle ?don?t care? or internal delays high impedance state (note 1) user generated signal valid data from input device cycle n fetch (s0) cycle (n+1) execute (s1) cycle (n+2) dma (s2) valid output 01234567012345670123456 clock tpa tpb machine cycle instruction dma out mrd mwr memory output data strobe (s2 ? tpb) cycle n cycle (n + 1) cycle (n + 2) dma (s2) execute (s1) fetch (s0) valid output valid data from memory note 1 memory read cycle memory read, write memory read cycle or non-memory cycle ?don?t care? or internal delays high impedance state user generated signal (note 1) (note 1) cdp1802a, cdp1802ac, cdp1802bc
3-17 figure 14. interrupt cycle timing waveforms performance curves figure 15. cdp1802a, ac typical maximum clock frequency as a function of temperature figure 16. cdp1802bc typical maximum clock frequency as a function of temperature machine cycle timing waveforms (propagation delays not shown) (continued) 01234567012345670123456 clock tpa tpb machine cycle instruction cycle n cycle (n + 1) cycle (n + 2) interrupt (s3) execute (s1) fetch (s0) mrd mwr interrupt memory output valid output note 1 memory read cycle memory read, write non-memory cycle or non-memory cycle ?don?t care? or internal delays high impedance state (note 1) ( internal) ie user generated signal 8 7 6 5 4 3 2 1 0 25 35 45 55 65 75 85 95 105 115 125 f cl , system maximum clock frequency (mhz) t a , ambient temperature ( o c) c l , load capacitance = 50pf v cc = v dd = 10v v cc = 5v, v dd = 10v v cc = v dd = 5v c l , load capacitance = 50pf v cc = v dd = 5v 8 7 6 5 4 3 2 1 0 25 35 45 55 65 75 85 95 105 115 125 f cl , system maximum clock frequency (mhz) t a , ambient temperature ( o c) cdp1802a, cdp1802ac, cdp1802bc
3-18 figure 17. typical transit ion time vs load capaci- tance for all types figure 18. cdp1802a, ac minimum output high (source) current characteristics figure 19. cdp1802a, ac minimum output low (sink) current characteristics figure 20. cdp1802bc minimum output high (source) current characteristics performance curves (continued) 400 350 300 250 200 150 100 50 0 0 25 50 75 100 125 150 175 200 t thl, t tlh , transition time (ns) c l , load capacitance (pf) t a = 25 o c v cc = v dd = 10v v cc = v dd = 5v v cc = v dd = 5v v cc = v dd = 10v t tlh t thl v gs , gate-to-voltage = -5v t a , ambient temperature = -40 o c to +85 o c -10v v ds , drain-to-source voltage (v) -10-9 -8-7-6 -5-4-3-2 -1 0 1 2 3 4 5 6 7 i oh , output high (source) current (ma) v gs , gate-to-source = 10v t a = -40 o c to +85 o c 5v v ds , drain-to-source voltage (v) i ol , output low (sink) current (ma) 012345678910 5 10 15 20 25 30 35 v gs , gate-to-voltage = -5v v ds , drain-to-source voltage (v) -5 -4 -3 -2 -1 0 1 2 3 4 i oh , output high (source) current (ma) cdp1802a, cdp1802ac, cdp1802bc
3-19 signal descriptions bus 0 to bus 7 (data bus) 8-bit bidirectional data bus lines. these lines are used for transferring data between the memory, the microprocessor, and i/o devices. n0 to n2 (i/o control lines) activated by an i/o instruction to signal the i/o control logic of a data transfer between memory and i/o interface. these lines can be used to issue command codes or device selec- tion codes to the i/o devices (independently or combined with the memory byte on the data bus when an i/o instruction is being executed). the n bits are low at all times except when an i/o instruction is being executed. during this time their state is the same as the corresponding bits in the n register. the direction of data flow is defined in the i/o instruction by bit n3 (internally) and is indicated by the level of the mrd signal. mrd = v cc : data from i/o to cpu and memory mrd = v ss : data from memory to i/o ef1 to ef4 (4 flags) these inputs enable the i/o controllers to transfer status information to the processor. the levels can be tested by the conditional branch instructions. they can be used in con- junction with the interrupt request line to establish inter- rupt priorities. these flags can also be used by i/o devices to ?call the attention? of the processor, in which case the pro- gram must routinely test the status of these flag(s). the flag(s) are sampled at the beginning of every s1 cycle. figure 21. cdp1802bc minimum output low (sink) current characteristics figure 22. typical change in propagation delay as a function of a change in load capacitance for all types note: idle = ?00? at m(0000), br anch = ?3707? at m(8107), cl = 50pf figure 23. typical power dissipation as a functio n of clock frequency for branch instruction and idle instruction for all types performance curves (continued) v gs , gate-to-source = 5v t a = -40 o c to +85 o c v ds , drain-to-source voltage (v) i ol , output low (sink) current (ma) 012345 5 10 20 150 125 100 75 50 25 0 25 50 100 150 200 ? t plh , ? t phl , ? propagation delay time (ns) ? c l , ? load capacitance (pf) t a = 25 o c v cc = v dd = 10v v cc = v dd = 5v v cc = v dd = 5v v cc = v dd = 10v ? t plh ? t phl note: any output except xtal t a = 25 o c p d , typical power dissipation for cdp1802d (mw) f cl , clock input frequency (mhz) 0.01 0.1 1 10 0.1 1 10 100 1000 v cc = v dd = 10v branch idle v cc = v dd = 5v cdp1802a, cdp1802ac, cdp1802bc
3-20 interrupt , dma-ln , dma-out (3 i/o requests) these inputs are sampled by the cpu during the interval between the leading edge of tpb and the leading edge of tpa. interrupt action - x and p are stored in t after executing current instruction; designator x is set to 2; designator p is set to 1; interrupt enable is reset to 0 (inhibit); and instruction execution is resumed. the interrupt action requires one machine cycle (s3). dma action - finish executing current instruction; r(0) points to memory area for data transfer; data is loaded into or read out of memory; and increment r(0). note: in the event of concurrent dma and interrupt requests, dma-ln has priority followed by dma-out and then interrupt. sc0, sc1, (2 state code lines) these outputs indicate that the cpu is: 1) fetching an instruction, or 2) executing an instruction, or 3) processing a dma request, or 4) acknowledging an interrupt request. the levels of state code are tabulated below. all states are valid at tpa. h = v cc , l = v ss . tpa, tpb (2 timing pulses) positive pulses that occur once in each machine cycle (tpb follows tpa). they are used by i/o controllers to interpret codes and to time interaction with the data bus. the trailing edge of tpa is used by the memory system to latch the higher-order byte of the 16-bit memory address. tpa is sup- pressed in idle when the cpu is in the load mode. ma0 to ma7 (8 memory address lines) in each cycle, the higher-order byte of a 16-bit cpu memory address appears on the memory address lines ma0-7 first. those bits required by the memory system can be strobed into external address latches by timing pulse tpa. the low order byte of the 16-bit address appears on the address lines after the termination of tpa. latching of all 8 higher-order address bits would permit a memory system of 64k bytes. mwr (write pulse) a negative pulse appearing in a memory-write cycle, after the address lines have stabilized. mrd (read level) a low level on mrd indicates a memory read cycle. it can be used to control three-state outputs from the addressed mem- ory which may have a common data input and output bus. if a memory does not have a three-state high-impedance output, mrd is useful for driving memory/bus separator gates. it is also used to indicate the direction of data transfer during an i/o instruction. for additional information see table 1. q single bit output from the cpu which can be set or reset under program control. during seq or req instruction exe- cution, q is set or reset between the trailing edge of tpa and the leading edge of tpb. clock input for externally generated single-phase clock. the clock is counted down internally to 8 clock pulses per machine cycle. xtal connection to be used with clock input terminal, for an exter- nal crystal, if the on-chip oscillator is utilized. the crystal is connected between terminals 1 and 39 (clock and xtal ) in parallel with a resistance (10m ? typ). frequency trimming capacitors may be required at terminals 1 and 39. for addi- tional information, see application note an6565. wait , clear (2 control lines) provide four control modes as listed in the following truth table: v dd , v ss , v cc (power levels) the internal voltage supply v dd is isolated from the input/output voltage supply v cc so that the processor may operate at maximum speed while interfacing with peripheral devices operating at lower voltage. v cc must be less than or equal to v dd . all outputs swing from v ss to v cc . the recom- mended input voltage swing is v ss to v cc . architecture the cpu block diagram is shown in figure 2. the principal feature of this system is a register array (r) consisting of six- teen 16-bit scratchpad registers. individual registers in the array (r) are designated (selected) by a 4-bit binary code from one of the 4-bit registers labeled n, p and x. the con- tents of any register can be directed to any one of the follow- ing three paths: 1. the external memory (multiplexed, higher-order byte first, on to 8 memory address lines). 2. the d register (either of the two bytes can be gated to d). 3. the increment/decrement circuit where it is increased or decreased by one and stored back in the selected 16-bit register. state type state code lines sc1 sc0 s0 (fetch) l l s1 (execute) l h s2 (dma) h l s3 (interrupt) h h clear wait mode llload lhreset hlpause h h run cdp1802a, cdp1802ac, cdp1802bc
3-21 the three paths, depending on the nature of the instruction, may operate independently or in various combinations in the same machine cycle. with two exceptions, cpu instruction consists of two 8- clock-pulse machine cycles. the first cycle is the fetch cycle, and the second - and third if necessary - are execute cycles. during the fetch cycle the four bits in the p designator select one of the 16 registers r(p) as the current program counter. the selected register r(p) contains the address of the mem- ory location from which the instruction is to be fetched. when the instruction is read out from the memory, the higher order 4 bits of the instruction byte are loaded into the register and the lower order 4 bits into the n register. the content of the program counter is automatically incremented by one so that r(p) is now ?pointing? to the next byte in the memory. the x designator selects one of the 16 registers r(x) to ?point? to the memory for an operand (or data) in certain alu or i/o operations. the n designator can perform the following five functions depending on the type of instruction fetched: 1. designate one of the 16 registers in r to be acted upon during register operations. 2. indicate to the i/o devices a command code or device selection code for peripherals. 3. indicate the specific operation to be executed during the alu instructions, types of test to be performed during the branch instruction, or the specific operation required in a class of miscellaneous instructions (70 - 73 and 78 - 7b). 4. indicate the value to be loaded into p to designate a new register to be used as the program counter r(p). 5. indicate the value to be loaded into x to designate a new register to be used as data pointer r(x). the registers in r can be assigned by a programmer in three different ways: as program count ers, as data pointers, or as scratchpad locations (data registers) to hold two bytes of data. program counters any register can be the main program counter; the address of the selected register is held in the p designator. other reg- isters in r can be used as subroutine program counters. by single instruction the contents of the p register can be changed to effect a ?call? to a subroutine. when interrupts are being serviced, register r(1) is used as the program counter for the user's interrupt servicing routine. after reset, and during a dma operation, r(0) is used as the program counter. at all other times the register designated as pro- gram counter is at the discretion of the user. data pointers the registers in r may be used as data pointers to indicate a location in memory. the register designated by x (i.e., r(x)) points to memory for the following instructions (see table 1). 1. alu operations f1 - f5, f7, 74, 75, 77 2. output instructions 61 through 67 3. input instructions 69 through 6f 4. certain miscellaneous instructions - 70 - 73, 78, 60, f0 the register designated by n (i.e., r(n)) points to memory for the ?load d from memory? instructions 0n and 4n and the ?store d? instruction 5n. the register designated by p (i.e., the program counter) is used as the data pointer for alu instructions f8 - fd, ff, 7c, 7d, 7f. during these instruction executions, the operation is referred to as ?data immediate?. another important use of r as a data pointer supports the built-in direct-memory-access (dma) function. when a dma-ln or dma-out request is received, one machine cycle is ?stolen?. this operation occurs at the end of the execute machine cycle in the current instruction. register r(0) is always used as the data pointer during the dma operation. the data is read from (dma-out) or written into (dma-ln) the memory location pointed to by the r(0) register. at the end of the transfer, r(0) is incremented by one so that the pro- cessor is ready to act upon the next dma byte transfer request. this feature in the 1800-series architecture saves a substantial amount of logic when fast exchanges of blocks of data are required, such as with magnetic discs or during crt-display-refresh cycles. data registers when registers in r are used to store bytes of data, four instructions are provided which allow d to receive from or write into either the higher-order or lower-order byte portions of the register designated by n. by this mechanism (together with loading by data immediate) program pointer and data pointer designations are initialized. also, this technique allows scratchpad registers in r to be used to hold general data. by employing increment or decrement instructions, such registers may be used as loop counters. the q flip-flop an internal flip-flop, q, can be set or reset by instruction and can be sensed by conditional branch instructions. the output of q is also available as a microprocessor output. cdp1802a, cdp1802ac, cdp1802bc
3-22 interrupt servicing register r(1) is always used as the program counter when- ever interrupt servicing is initiated. when an interrupt request occurs and the interrupt is allowed by the program (again, nothing takes place until the completion of the cur- rent instruction), the contents of the x and p registers are stored in the temporary register t, and x and p are set to new values; hex digit 2 in x and hex digit 1 in p. interrupt enable is automatically deactivated to inhibit further inter- rupts. the user's interrupt routine is now in control; the con- tents of t may be saved by means of a single instruction (78) in the memory location pointed to by r(x). at the conclusion of the interrupt, the user's routine may restore the pre-inter- rupted value of x and p with a single instruction (70 or 71). the interrupt enable flip-flop can be activated to permit fur- ther interrupts or can be disabled to prevent them. cpu register summary cdp1802 control modes the wait and clear lines provide four control modes as listed in the following truth table: the function of the modes are defined as follows: load holds the cpu in the idle execution state and allows an i/o device to load the memory without the need for a ?bootstrap? loader. it modifies the idle condition so that dma-ln opera- tion does not force execution of the next instruction. reset registers l, n, q are reset, le is set and 0?s (vss) are placed on the data bus. tpa and tpb are suppressed while reset is held and the cpu is placed in s1. the first machine cycle after ter- mination of reset is an initialization cycle which requires 9 clock pulses. during this cycle the cpu remains in s1 and register x, p, and r(0) are reset. interrupt and dma servicing are sup- pressed during the initialization cycle. the next cycle is an s0, s1, or an s2 but never an s3. with the use of a 71 instruction followed by 00 at memory locations 0000 and 0001, this feature may be used to reset ie, so as to preclude interrupts until ready for them. power-up reset can be realized by connecting an rc network directly to the clear pin, since it has a schmitt trig- gered input, see figure 24. pause stops the internal cpu timing generator on the first negative high-to-low transition of the input clock. the oscillator contin- ues to operate, but subsequent clock transitions are ignored. run may be initiated from the pause or reset mode functions. if initiated from pause, the cpu resumes operation on the first negative high-to-low transition of the input clock. when initi- ated from the reset operation, the first machine cycle follow- ing reset is always the initialization cycle. the initialization cycle is then followed by a dma (s2) cycle or fetch (s0) from location 0000 in memory. run-mode state transitions the cpu state transitions when in the run and reset modes are shown in figure 25. each machine cycle requires the same period of time, 8 clock pulses, except the initializa- tion cycle, which requires 9 clock pulses. the execution of an instruction requires either two or three machine cycles, s0 followed by a single s1 cycle or two s1 cycles. s2 is the response to a dma request and s3 is the interrupt response. table 2 shows the conditions on data bus and memory address lines during all machine states. instruction set the cpu instruction summary is given in table 1. hexadeci- mal notation is used to refer to the 4-bit binary codes. in all registers bits are numbered from the least significant bit (lsb) to the most significant bit (msb) starting with 0. r(w): register designated by w, where w = n or x, or p r(w).0: lower order byte of r(w) r(w).1: higher order byte of r(w) operation notation m(r(n)) d; r(n) + 1 r(n) this notation means: the memory byte pointed to by r(n) is d 8 bits data register (accumulator) df 1-bit data flag (alu carry) b 8 bits auxiliary holding register r 16 bits 1 of 16 scratchpad registers p 4 bits designates which register is program counter x 4 bits designates which register is data pointer n 4 bits holds low-order instruction digit i 4 bits holds high-order instruction digit t 8 bits holds old x, p after interrupt (x is high nibble) le 1-bit interrupt enable q 1-bit output flip-flop clear wait mode llload l h reset h l pause h h run clear v cc r s c cdp1802 3 the rc time constant should be greater than the oscillator start-up time (typically 20ms) figure 24. reset diagram cdp1802a, cdp1802ac, cdp1802bc
3-23 loaded into d, and r(n) is incremented by 1. figure 25. state transition diagram table 1. instruction summary (see notes) instruction mnemonic op code operation memory reference load via n ldn 0n m(r(n)) d; for n not 0 load advance lda 4n m(r(n)) d; r(n) + 1 r(n) load via x ldx f0 m(r(x)) d load via x and advance ldxa 72 m(r(x)) d; r(x) + 1 r(x) load immediate ldl f8 m(r(p)) d; r(p) + 1 r(p) store via n str 5n d m(r(n)) store via x and decrement stxd 73 d m(r(x)); r(x) - 1 r(x) register operations increment reg n inc 1n r(n) + 1 r(n) decrement reg n dec 2n r(n) - 1 r(n) increment reg x irx 60 r(x) + 1 r(x) get low reg n glo 8n r(n).0 d put low reg n plo an d r(n).0 get high reg n ghl 9n r(n).1 d put high reg n phi bn d r(n).1 logic operations (note 1) or or f1 m(r(x)) or d d or immediate orl f9 m(r(p)) or d d; r(p) + 1 r(p) s2 dma s1 reset s1 execute s0 fetch s3 int s1 init dma dma dma ? int dma dma idle ? dma ? int force s1 (long branch, dma ? idle ? int dma dma int ? dma long skip, nop, etc.) priority: force s0, s1 dma in dma out int int ? dma cdp1802a, cdp1802ac, cdp1802bc
3-24 exclusive or xor f3 m(r(x)) xor d d exclusive or immediate xri fb m(r(p)) xor d d; r(p) + 1 r(p) and and f2 m(r(x)) and d d and immediate anl fa m(r(p)) and d d; r(p) + 1 r(p) shift right shr f6 shift d right, lsb(d) df, 0 msb(d) shift right with carry shrc 76 (note 2) shift d right, lsb(d) df, df msb(d) ring shift right rshr 76 (note 2) shift d right, lsb(d) df, df msb(d) shift left shl fe shift d left, msb(d) df, 0 lsb(d) shift left with carry shlc 7e (note 2) shift d left, msb(d) df, df lsb(d) ring shift left rshl 7e (note 2) shift d left, msb(d) df, df lsb(d) arithmetic operations (note 1) add add f4 m(r(x)) + d df, d add immediate adl fc m(r(p)) + d df, d; r(p) + 1 r(p) add with carry adc 74 m(r(x)) + d + df df, d add with carry, immediate adcl 7c m(r(p)) + d + df df, d; r(p) + 1 r(p) subtract d sd f5 m(r(x)) - d df, d subtract d immediate sdl fd m(r(p)) - d df, d; r(p) + 1 r(p) subtract d with borrow sdb 75 m(r(x)) - d - (not df) df, d subtract d with borrow, immediate sdbl 7d m(r(p)) - d - (not df) df, d; r(p) + 1 r(p) subtract memory sm f7 d-m(r(x)) df, d subtract memory immediate sml ff d-m(r(p)) df, d; r(p) + 1 r(p) subtract memory with borrow smb 77 d-m(r(x))-(not df) df, d subtract memory with borrow, immedi- ate smbl 7f d-m(r(p))-(not df) df, d; r(p) + 1 r(p) branch instructions - short branch short branch br 30 m(r(p)) r(p).0 no short branch (see skp) nbr 38 (note 2) r(p) + 1 r(p) short branch if d = 0 bz 32 if d = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if d not 0 bnz 3a if d not 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if df = 1 bdf 33 (note 2) if df = 1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if pos or zero bpz short branch if equal or greater bge short branch if df = 0 bnf 3b (note 2) if df = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if minus bm short branch if less bl short branch if q = 1 bq 31 if q = 1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if q = 0 bnq 39 if q = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) table 1. instruction summary (see notes) (continued) instruction mnemonic op code operation cdp1802a, cdp1802ac, cdp1802bc
3-25 short branch if ef1 = 1 (ef1 = v ss ) b1 34 if ef1 =1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef1 = 0 (ef1 = v cc ) bn1 3c if ef1 = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef2 = 1 (ef2 = v ss ) b2 35 if ef2 = 1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef2 = 0 (ef2 = v cc ) bn2 3d if ef2 = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef3 = 1 (ef3 = v ss ) b3 36 if ef3 = 1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef3 = 0 (ef3 = v cc ) bn3 3e if ef3 = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef4 = 1 (ef4 = v ss ) b4 37 if ef4 = 1, m(r(p)) r(p).0, else r(p) + 1 r(p) short branch if ef4 = 0 (ef4 = v cc ) bn4 3f if ef4 = 0, m(r(p)) r(p).0, else r(p) + 1 r(p) branch instructions - long branch long branch lbr c0 m(r(p)) r(p). 1, m(r(p) + 1) r(p).0 no long branch (see lskp) nlbr c8 (note 2) r(p) = 2 r(p) long branch if d = 0 lbz c2 lf d = 0, m(r(p)) r(p).1, m(r(p) +1) r(p).0, else r(p) + 2 r(p) long branch if d not 0 lbnz ca if d not 0, m(r(p)) r(p).1, m(r(p) + 1) r(p).0, else r(p) + 2 r(p) long branch if df = 1 lbdf c3 lf df = 1, m(r(p)) r(p).1, m(r(p) + 1) r(p).0, else r(p) + 2 r(p) long branch if df = 0 lbnf cb if df = 0, m(r(p)) r(p).1, m(r(p) + 1) r(p).0, else r(p) + 2 r(p) long branch if q = 1 lbq c1 if q = 1, m(r(p)) r(p).1, m(r(p) + 1) r(p).0, else r(p) + 2 r(p) long branch lf q = 0 lbnq c9 lf q = 0, m(r(p)) r(p).1, m(r(p) + 1) r(p).0 eise r(p) + 2 r(p) skip instructions short skip (see nbr) skp 38 (note 2) r(p) + 1 r(p) long skip (see nlbr) lskp c8 (note 2) r(p) + 2 r(p) long skip if d = 0 lsz ce if d = 0, r(p) + 2 r(p), else continue long skip if d not 0 lsnz c6 if d not 0, r(p) + 2 r(p), else continue long skip if df = 1 lsdf cf if df = 1, r(p) + 2 r(p), else continue long skip if df = 0 lsnf c7 if df = 0, r(p) + 2 r(p), else continue long skip lf q = 1 lsq cd if q = 1, r(p) + 2 r(p), else continue long skip if q = 0 lsnq c5 if q = 0, r(p) + 2 r(p), else continue long skip if le = 1 lsle cc if ie = 1, r(p) + 2 r(p), else continue control instructions idle ldl 00 (note 3) wait for dma or interrupt; m(r(0)) bus no operation nop c4 continue set p sep dn n p set x sex en n x set q seq 7b 1 q table 1. instruction summary (see notes) (continued) instruction mnemonic op code operation cdp1802a, cdp1802ac, cdp1802bc
3-26 reset q req 7a 0 q save sav 78 t m(r(x)) push x, p to stack mark 79 (x, p) t; ( x , p ) m(r(2)), then p x; r(2) - 1 r(2) return ret 70 m(r(x)) (x, p); r(x) + 1 r(x), 1 le disable dls 71 m(r(x)) (x, p); r(x) + 1 r(x), 0 le input - output byte transfer output 1 out 1 61 m(r(x)) bus; r(x) + 1 r(x); n lines = 1 output 2 out 2 62 m(r(x)) bus; r(x) + 1 r(x); n lines = 2 output 3 out 3 63 m(r(x)) bus; r(x) + 1 r(x); n lines = 3 output 4 out 4 64 m(r(x)) bus; r(x) + 1 r(x); n lines = 4 output 5 out 5 65 m(r(x)) bus; r(x) + 1 r(x); n lines = 5 output 6 out 6 66 m(r(x)) bus; r(x) + 1 r(x); n lines = 6 output 7 out 7 67 m(r(x)) bus; r(x) + 1 r(x); n lines = 7 input 1 inp 1 69 bus m(r(x)); bus d; n lines = 1 input 2 inp 2 6a bus m(r(x)); bus d; n lines = 2 input 3 inp 3 6b bus m(r(x)); bus d; n lines = 3 input 4 inp 4 6c bus m(r(x)); bus d; n lines = 4 input 5 inp 5 6d bus m(r(x)); bus d; n lines = 5 input 6 inp 6 6e bus m(r(x)); bus d; n lines = 6 input 7 inp 7 6f bus m(r(x)); bus d; n lines = 7 table 1. instruction summary (see notes) (continued) instruction mnemonic op code operation cdp1802a, cdp1802ac, cdp1802bc
3-27 notes: (for table 1) 1. the arithmetic operations and the shift instructions are the only instructions that can alter the df. after an add instruction: df = 1 denotes a carry has occurred df = 0 denotes a carry has not occurred after a subtract instruction: df = 1 denotes no borrow. d is a true positive number df = 0 denotes a borrow. d is two?s complement the syntax ?-(not df)? denotes the subtraction of the borrow. 2. this instruction is associated with more than one mnemonic. each mnemonic is individually listed. 3. an idle instruction initiates a repeating s1 cycle. the processor will continue to idle until an i/o request (interrupt , dma-ln , or dma- out ) is activated. when the request is acknowledged, the idle cycle is terminated and the i/o request is serviced, and then normal oper ation is resumed. 4. long-branch, long-skip and no op instructions require three cycles to complete (1 fetch + 2 execute). long-branch instructions are three bytes l ong. the first byte specifies the condition to be tested; and the second and third by te, the branching address. the long-branch instructions can: a. branch unconditionally b. test for d = 0 or d 0 c. test for df = 0 or df = 1 d. test for q = 0 or q = 1 e. effect an unconditional no branch if the tested condition is met, then branching takes place; the branching address bytes are loaded in the high-and-low order by tes of the current program counter, respectively. this operation effects a branch to any memory location. if the tested condition is not met, the branching address bytes are skipped over, and the next instruction in sequence is fetch ed and exe- cuted. this operation is taken for the case of unconditional no branch (nlbr). 5. the short-branch instructions are two bytes long. the first by te specifies the condition to be tested, and the second specifi es the branching address. the short branch instruction can: a. branch unconditionally b. test for d = 0 or d 0 c. test for df = 0 or df = 1 d. test for q = 0 or q = 1 e. test the status (1 or 0) of the four ef flags f. effect an unconditional no branch if the tested condition is met, then branching takes place; t he branching address byte is loaded in to the low-order byte positi on of the current program counter. this effects a branch within the current 256-byte page of the memory, i.e., the page which holds the b ranching address. if the tested condition is not met, the branching addres s byte is skipped over, and the next instruction in sequence i s fetched and executed. this same action is taken in the case of unconditional no branch (nbr). 6. the skip instructions are one byte long. there is one un conditional short-skip (skp) and eight long-skip instructions. the unconditional short-skip instruction takes 2 cycles to comple te (1 fetch + 1 execute). its ac tion is to skip over the byte following it. then the next instruction in sequence is fetched and executed. th is skp instruction is identical to the unconditional no-branch instruc- tion (nbr) except that the skipped-over by te is not considered part of the program. the long-skip instructions take three cycles to complete (1 fetch + 2 execute). they can: a. skip unconditionally b. test for d = 0 or d 0 c. test for df = 0 or df = 1 d. test for q = 0 or q = 1 e. test for ie = 1 if the tested condition is met, then long skip takes place; the cu rrent program counter is increm ented twice. thus two bytes ar e skipped over, and the next instruction in sequence is fetched and executed. if the tested condition is not met, then no action is taken . execution is continued by fetching the next instruction in sequence. table 1. instruction summary (see notes) (continued) instruction mnemonic op code operation cdp1802a, cdp1802ac, cdp1802bc
3-28 table 2. conditions on data bus and memory address lines during all machine states state i n symbol operation data bus memory address mrd mwr n lines notes s1 reset 0 i, n, q, x, p; 1 le 00 xxxx 1 1 0 1 initialize, not programmer accessible 0000 r00xxxx1102 s0 fetch mrp l, n; rp + 1 rp mrp rp 0 1 0 3 s1 0 0 ldl idle mr0 ro 0 1 0 4, fig. 8 01 - f ldn mrn d mrn rn 0 1 0 fig. 8 1 0 - f inc rn + 1 rn float rn 1 1 0 fig. 6 2 0 - f dec rn - 1 rn float rn 1 1 0 fig. 6 3 0 - f short branch taken: mrp rp.0 not taken; rp + 1 rp mrp rp 0 1 0 fig. 8 40 - f lda mrn d; rn + 1 rn mrn rn 0 1 0 fig. 8 50 - f str d mrn d rn 1 0 0 fig. 7 60 irx rx + 1 rx mrx rx 0 1 0 fig. 7 61 out 1 mrx bus; rx + 1 rx mrx rx 0 1 1 fig. 11 2out 2 2fig. 11 3out 3 3fig. 11 4out 4 4fig. 11 5out 5 5fig. 11 6out 6 6fig. 11 7out 7 7fig. 11 9 inp 1 bus mrx, d data from i/o device rx 1 0 1 fig. 10 ainp 2 2fig. 10 binp 3 3fig. 10 cinp 4 4fig. 10 dinp5 5fig. 10 einp6 6fig. 10 finp7 7fig. 10 7 0 ret mrx (x, p); rx + 1 rx; 1 le mrx rx 0 1 0 fig. 8 1 dls mrx (x, p); rx + 1 rx; 0 le mrx rx 0 1 0 fig. 8 2 ldxa mrx d; rx + 1 rx mrx rx 0 1 0 fig. 8 3stxdd mrx; rx - 1 rx d rx 1 0 0 fig. 7 4 adc mrx + d + df df, d mrx rx 0 1 0 fig. 8 5 sdb mrx - d - dfn df, d mrx rx 0 1 0 fig. 8 6 shrc lsb(d) df; df msb(d) float rx 1 1 0 fig. 6 7 smb d - mrx - dfn df, d mrx rx 0 1 0 fig. 8 8savt mrx t rx 1 0 0 fig. 7 cdp1802a, cdp1802ac, cdp1802bc
3-29 s1 7 9 mark (x, p) t, mr2; p x; r2 - 1 r2 tr2100fig. 7 areq0 q float rp 1 1 0 fig. 6 bseq1 q float rp 1 1 0 fig. 6 c adcl mrp + d + df df, d; rp + 1 mrp rp 0 1 0 fig. 8 d sdbl mrp - d - dfn df, d; rp + 1 mrp rp 0 1 0 fig. 8 e shlc msb(d) df; df lsb(d) float rp 1 1 0 fig. 6 f smbl d - mrp - dfn df, d; rp + 1 mrp rp 0 1 0 fig. 8 8 0 - f glo rn.0 d rn.0 rn 1 1 0 fig. 6 9 0 - f ghl rn.1 d rn.1 rn 1 1 0 fig. 6 a0 - f plo d rn.0 d rn 1 1 0 fig. 6 b0 - f phi d rn.1 d rn 1 1 0 fig. 6 s1#1 c 0 - 3, 8 - b long branch taken: mrp b; rp + 1 rp mrp rp 0 1 0 fig. 9 #2 taken: b rp.1; mrp rp.0 m(rp + 1) rp + 1 0 1 0 fig. 9 s1#1 not taken: rp + 1 rp mrp rp 0 1 0 fig. 9 #2 not taken: rp + 1 rp m(rp + 1) rp + 1 0 1 0 fig. 9 s1#1 5 6 7 c d e f long skip taken: rp + 1 rp mrp rp 0 1 0 fig. 9 #2 taken: rp + 1 rp m(rp + 1) rp + 1 0 1 0 fig. 9 s1#1 not taken: no operation mrp rp 0 1 0 fig. 9 #2 not taken: no operation mrp rp 0 1 0 fig. 9 s1#1 4 nop no operation mrp rp 0 1 0 fig. 9 #2 no operation mrp rp 0 1 0 fig. 9 s1 d 0 - f sep n pnnrn110fig. 6 e0 - f sex n xnnrn110fig. 6 s1 f 0 ldx mrx d mrx rx 0 1 0 fig. 8 1 2 3 4 5 7 or and xor add sd sm mrx or d d mrx and d d mrx xor d d mrx + d df, d mrx - d df, d d - mrx df, d mrx rx 0 1 0 fig. 8 6shrlsb(d) df; 0 msb(d) float rx 1 1 0 fig. 6 table 2. conditions on data bus and memory address lines during all machine states (continued) state i n symbol operation data bus memory address mrd mwr n lines notes cdp1802a, cdp1802ac, cdp1802bc
3-30 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com operating and handling considerations handling all inputs and outputs of intersil cmos devices have a net- work for electrostatic protection during handling. operating operating voltage - during operation near the maximum supply voltage limit care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply rip- ple, or ground noise; any of these conditions must not cause v dd - v ss to exceed the absolute maximum rating. input signals - to prevent damage to the input protection circuit, input signals should never be greater than v dd nor less than v ss . input currents must not exceed 10ma even when the power supply is off. unused inputs - a connection must be provided at every input terminal. all unused input terminals must be connected to either v dd or v ss , whichever is appropriate. output short circuits - shorting of outputs to v dd or v ss may damage cmos devices by exceeding the maximum device dissipation. s1 f 8 ldl mrp d; rp + 1 rp mrp rp 0 1 0 fig. 8 9orlmrp or d d; rp + 1 rp a anl mrp and d d; rp + 1 rp b xrl mrp xor d d; rp + 1 rp cadlmrp + d df, d; rp + 1 rp d sdl mrp - d df, d; rp + 1 rp f sml d - mrp df, d; rp +1 rp eshlmsb(d) df; 0 lsb(d) float rp 1 1 0 fig. 6 s2 dma in bus mr0; r0 + 1 r0 data from i/o device r0 1 0 0 6, fig. 12 dmaout mr0 bus; r0 + 1 r0 mr0 r0 0 1 0 6, fig. 13 s3 interrupt x, p t; 0 le, 1 p; 2 x float rn 1 1 0 fig. 14 s1 load idle (clear , walt = 0) m(r0 - 1) r0 - 1 0 1 0 5, fig. 8 notes: 1. le = 1, tpa, tpb suppressed, state = s1. 2. bus = 0 for entire cycle. 3. next state always s1. 4. wait for dma or interrupt. 5. suppress tpa, wait for dma. 6. in request has priority over out request. 7. see timing waveforms, figure 5 through figure 14 for machine cycles. table 2. conditions on data bus and memory address lines during all machine states (continued) state i n symbol operation data bus memory address mrd mwr n lines notes

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